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Revision 1.4
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AS5132
Datasheet - Electrical Characteristics
6.5 DC Characteristics of Digital Inputs
CMOS Inputs COM/INC, CSN, CLK, DIO, DIR
6.6 DC Characteristics of Digital Outputs
CMOS Outputs S, U_A, V_B, W_I, PWM, DIO
6.7 Timing Characteristics
Symbol
Parameter
Min
Typ
Max
Units
Note
VIH
High level input voltage
0.7*VDDP
VDDP
V
COM/INC refer to VDD
VIL
Low level input voltage
0
0.3*VDDP
V
ILEAK
Input leakage current
1
礎
Symbol
Parameter
Min
Typ
Max
Units
Note
V
OH
High level output voltage
VDDP-0.5
VDDP
V
PWM and S have 8mA output load,
DIO has 4mA output load.
VDD-0.5
VDD
U_A, V_B, W_I have 4mA output load.
V
OL
Low level output voltage
0
VSS+0.4
V
PWM and S have 8mA output load,
DIO, U_A, V_B, W_I has 4mA output load.
CL
Capacitive load
35
pF
Symbol
Parameter
Conditions
Min
Typ
Max
Units
f
CLK
Clock Frequency
Normal operation
5
6
MHz
f
CLKP
Clock Frequency programming
During OTP programming
200
650
kHz
t1
Chip select to positive edge of CLK
15
ns
t2
Setup time command bit,
Data valid to positive edge of CLK
30
ns
t3
Hold time command bit,
Data valid after positive edge of CLK
30
ns
t4
Float time,
Last command bit to negative edge of CLK
30
ns
t5
Transfer time,
Negative edge to valid data
30
ns
t6
Last CLK to positive edge CSN
30
ns
t
CLK
Clock period
167
200
ns
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